Semiconductor memory devices which have an address terminal (pin) for receiving an address signal and a data terminal (pin) for receiving or outputting a data signal, for common use, have been hitherto known. In these devices, the address signal and the data signal are multiplexed for use, so that reduction of the number of the terminals is effected (refer to Patent Document 1 which will be described later, for example). FIG. 8 is a diagram showing a configuration of a semiconductor memory device described in the hereinafter described Patent Document 1.
As shown in FIG. 8, this static type RAM (random access memory) includes a static memory cell array 4, a row decoder 5, a column decoder 6, a read/write buffer (also referred to as a “read/write amplifier”) 7, latch circuits 8A to 8C, an output buffer 9, address terminals A14-8 for receiving upper seven bits A14 to A8 of an address signal, an address and data common terminals 2 shared by lower eight bits A7 to A0 of the address signal and parallel eight-bit D7 to D0 of a data signal, control terminals for receiving a write enable signal/WE for controlling a write, an output enable signal/OE for controlling data reading, and a chip select signal/CS for controlling chip activation, respectively. In the configuration shown in FIG. 8, A7 to A0 of the address signal are latched by the latch circuit 8B at a falling edge of the chip select signal /CS and latched address signal is supplied to the column decoder 6. Until the chip select signal /CS rises, the common terminal 2 functions as the data terminal. During a period in which the write enable signal /WE is inactive (high), the latch circuit 8A outputs A14 to A8 of the address signal with alteration. When the write enable signal /WE becomes active (low), the latch circuit 8A holds its output value. The latch circuit 8C samples D7-D0 of the data signal at the common terminals 2 at a transition edge of the write enable signal /WE from a high level to a low level.
FIGS. 9A and 9B are timing diagrams for explaining timing operations of a read cycle and a write cycle of the semiconductor memory device shown in FIG. 8, respectively. Referring to FIG. 8 and FIG. 9A, at the time of a read, A0 to A14 of the 15 bit address signal are supplied from a CPU not shown through an address bus, and the chip select signal /CS is made active (low)(at a time t1). Then, the lower 8 bits of the address signal A7 to A0 are latched by the latch circuit 8B. Thereafter, the common terminal 2 is brought to a high impedance state and then the output enable signal /OE is made active (low). Eight-bit read data D7 to D0 are thereby output in parallel from the output buffer 9 to the common terminal 2 at a time t2.
Next, referring to FIGS. 8 and 9B, at the time of a write, the A0 to A14 of the address signal are output from the CPU not shown through the address bus, and the chip select signal /CS is made low (at a time t3). Then, the lower eight bits of the address signal A7 to A0 are latched by the latch circuit 8B. Thereafter, eight-bit write data D7 to D0 are supplied to the common terminals 2 from the CPU. At a time t4, the write enable signal /WE is activated (made low), so that D7 to D0 are latched by the latch circuit 8C, and writing of the eight-bit data D7 to D0 to a selected memory cell is performed through the write buffer 7. The Patent Document 1 describes a configuration of a dynamic type RAM as well, in which by having the address terminals and the data terminals for common use, reduction of the number of terminals is effected. In the dynamic-type RAM, a lower address is latched at a fall of a low address strobe signal /RAS and an upper address is latched at a fall of a column address strobe signal /CAS, for supply to a row decoder and a column decoder, respectively.
Recently, in addition to a calling function, multi-media functions such as image transmission by an electronic mail, distribution of music and moving pictures using accesses to the Internet are included in portable terminals, so that higher performance and larger capacity of a memory mounted therein are demanded. As a semiconductor memory device for the portable terminal, of which the larger capacity and the higher performance are demanded, a semiconductor memory that includes a page mode function and enabled a high-speed page read has been developed (refer to a hereinafter described Non-patent Document 1, for example). Further, a DRAM (also referred to as a “pseudo-SRAM”) that includes an auto precharging function for simulating an SRAM (static random access memory) and can read data in a burst mode and a page mode is also known (refer to Patent Document 2).
An overview of a page mode operation of a semiconductor memory device compliant with an asynchronous SRAM interface for the portable terminal will be described below. In the page mode (referred to as a “high-speed page mode”), a plurality of words within the same page are consecutively accessed. FIG. 10 is a diagram showing operation timing at the time of a read in the page mode, and is based on FIG. 3, page 26 of the hereinafter described Non-patent Document 1. At the beginning of a read mode, a chip enable signal CE1 is made active (low), and the output enable signal /OE is also made low (low). The write enable signal /WE is kept inactive (high) because of the read mode. In the example shown in FIG. 10, an address within a page (with the page size thereof being eight words) is specified by the address signal A0 to A2 indicating the lower three bits out of 21 bit address signal A0 to A20, and eight words of plural read data signals within the same page are consecutively output from a data terminal DQ. As described above, in the page mode, the performance when collective data is consecutively read is improved. In the example in FIG. 10, a page address time tpAA, which is an access time from a transition of a page address to output of corresponding word data to the data terminal DQ is set to several tens of nanoseconds, for example. Signals UB and LB in FIG. 10 are the signals for controlling upper byte/lower byte access, and is made low for word-based read and write, for example. Since they are the signals that are not directly related to the subject of the present invention, their description will be omitted.
[Patent Document 1]
JP Patent Kokai Publication No. JP-A-2-177190 (Pages 3–4, FIGS. 2–6)
[Patent Document 2]
JP Patent Kokai JP-P2003-233989A (Pages 3–4, FIGS. 1–2)
[Non-patent Document 1]
“MEMORY FOR CELLULAR PHONE APPLICATIONS MOBILE FCRAM (R) EQUIPPED WITH HIGH-SPEED PAGE MODE MB82DPS02183B/MB82DP02322A”, FUJITSU ELECTRIC DEVICES NEWS FIND Vol. 20, No. 6, 2002, Internet URL<http://edevice.fujitsu.com/jp/catalog/find/20-6/pdf/24-27.pdf> (searched on Sep. 11, 2003)